Coverage in Monitor

UVM
1

Why does my coverage inside the monitor is not working ? Showing 0 % coverage
here’s the link - EDA Playground

2

Hi Avii,
In your monitor,

  1. In cover points, you are not taking data items using the handle of your alu_sequence_items like item.reset, item.a, etc.
  2. Coverpoint for reset won’t get covered because you have not declared reset in your sequence items.
  3. In the run phase task, you are sampling coverage before calling the write method because none of the bins will hit, so sample after calling the write method for collected items.

Updated code:- EDA Playground

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3

Please pay attention to the monitor code,
you are assigning the values from the interface into the item defined on line:269…
You are not assigning it into the local members of the monitor class.
Your cover-points are defined based on the values of these local monitor class members.

Would suggest to read the verification academy “coverage cookbook”,
to get a better grasp of System-Verilog coverage practices and constructs.

Link: Coverage Cookbook | Cookbook

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