Cover properties under generate

Coverage
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1

I’m trying to cover a property which accepts input arguments. I want to call ‘cover property’ under nested for loops to pass different arguments to the property. But at the same time i want to avoid a select combination of my nested for loop iterations. I tried using ‘continue’ to skip those iterations. But SystemVerilog doesn’t let me do this. Any ideas on how to overcome this? I could try negating the boolean expression and guard the cover property instead. But wondering if there’s an alternate solution

generate 
  for (genvar i=0; i<8; i++) begin
    for (genvar j=0; j<8; j++) begin
      // Want to skip covering property when i=1 and j=1.
      // But the below line didn't work.
      // if(i==1 && j==1) continue;
      p_cover_label: cover property (prop_name(i, j));
    end
  end
endgenerate
2

In reply to vignesh.kannan:

 for (genvar i=0; i<8; i++) begin
    for (genvar j=0; j<8; j++) begin
      if(i!=1 || j!=1) 
         p_cover_label: cover property (prop_name(i, j));
    end
  end