hi i’am facing this error,
I’am quite confused because the object handle which i’m casting is received correctly and the i’ve created the handle memory in build phase
my intention was to create a bin for enum value “word” if address is word aligned so i went with “with” clause,
** Fatal: (SIGSEGV) Bad handle or reference.
# Time: 0 ns Iteration: 10 Process: /uvm_pkg::uvm_phase::m_run_phases/#FORK#2213_7fe7f42bf3e File: apb_slave.sv
# Fatal error in Function ahb_size::#solve_bin_#word_item_#ahb_size##28 at coverage.sv line 28
#
# HDL call sequence:
# Stopped at coverage.sv 28 Function ahb_size::#solve_bin_#word_item_#ahb_size##28 - -
# called from coverage.sv 27 Function #cg1#::new - -
# called from coverage.sv 54 Function coverage::new - -
# called from /usr/share/questa/questasim/linux_x86_64/../verilog_src/uvm-1.2/src/base/uvm_registry.svh 66 Function uvm_component_registry::create_component - -
# called from /usr/share/questa/questasim/linux_x86_64/../verilog_src/uvm-1.2/src/base/uvm_factory.svh 1305 Function uvm_default_factory::create_component_by_type - -
# called from /usr/share/questa/questasim/linux_x86_64/../verilog_src/uvm-1.2/src/base/uvm_registry.svh 115 Function create - -
# called from env.sv 42 Function env::build_phase - -
# called from /usr/share/questa/questasim/linux_x86_64/../verilog_src/uvm-1.2/src/base/uvm_common_phases.svh 65 Function uvm_build_phase::exec_func - -
# called from /usr/share/questa/questasim/linux_x86_64/../verilog_src/uvm-1.2/src/base/uvm_topdown_phase.svh 111 Function uvm_topdown_phase::execute - -
# called from /usr/share/questa/questasim/linux_x86_64/../verilog_src/uvm-1.2/src/base/uvm_topdown_phase.svh 78 Function uvm_topdown_phase::traverse - -
# called from /usr/share/questa/questasim/linux_x86_64/../verilog_src/uvm-1.2/src/base/uvm_topdown_phase.svh 95 Function uvm_topdown_phase::traverse - -
# called from /usr/share/questa/questasim/linux_x86_64/../verilog_src/uvm-1.2/src/base/uvm_topdown_phase.svh 95 Function uvm_topdown_phase::traverse - -
# called from /usr/share/questa/questasim/linux_x86_64/../verilog_src/uvm-1.2/src/base/uvm_phase.svh 1390 Task uvm_phase::execute_phase - -
# called from /usr/share/questa/questasim/linux_x86_64/../verilog_src/uvm-1.2/src/base/uvm_phase.svh 2213 Task m_run_phases - -
# Fatal error reported during simulation. Coverage report is disabled. Please look above output for the fatal error message(s).
#
# End time: 10:43:23 on Feb 06,2024, Elapsed time: 0:00:02
# Errors: 1, Warnings: 0
# *** Summary *********************************************
# qrun: Errors: 0, Warnings: 0
# vlog: Errors: 0, Warnings: 8
# vopt: Errors: 0, Warnings: 8
# vsim: Errors: 1, Warnings: 0
# Totals: Errors: 1, Warnings: 16,
////////////////////////////////////////////////////////////////////////////////////////////////////
this is my code,
//`uvm_analysis_imp_decl(_apb)
//`uvm_analysis_imp_decl(_ahb)
`uvm_analysis_imp_decl(_mem)
class coverage extends uvm_component;
local bit[`ADDR_WIDTH - 1 : 0]in_addr;
local bit[`ADDR_WIDTH - 1 : 0]l_start_reg;
local bit[`ADDR_WIDTH - 1 : 0]l_end_reg;
local bit[1 : 0] l_ctrl_reg;
uvm_analysis_imp_apb #(apb_transfer,coverage) apb_imp;
uvm_analysis_imp_ahb #(ahb_m_seq_item, coverage) ahb_imp;
uvm_analysis_imp_mem #(mem_seq_item, coverage) mem_imp;
mem_seq_item mem_item;
ahb_m_seq_item ahb_item;
apb_transfer apb_item;
covergroup cg1;
ahb_size: coverpoint ahb_item.hsize{bins word = {WORD} with (ahb_item.haddr[1 : 0] == 'b00);
bins def = default;
}
ahb_addr : coverpoint ahb_item.haddr{bins incr4_trans = (in_addr => in_addr + 4 => in_addr + 8 => in_addr +12 );// with (ahb_item.hburst == INCR4);
bins def = default;
}
ahb_htrans : coverpoint ahb_item.htrans[0] {bins trans = (NONSEQ => SEQ => SEQ => SEQ) ;//with ((ahb_item.hburst == INCR4)||(ahb_item.hburst == WRAP4));
bins def = default;
}
apb_addr : coverpoint apb_item.paddr{bins start_reg = {0};
bins end_reg = {4};
bins ctrl_reg = {8};
bins def = default;
}
apb_data : coverpoint apb_item.pwdata{bins ctrl[4] = {[0 : 3]} with (apb_item.paddr == 'h8);
bins start_addr = {apb_item.pwdata} with (apb_item.paddr == 'h0);
bins end_addr = {apb_item.pwdata} with (apb_item.paddr == 'h4);
}
endgroup : cg1
`uvm_component_utils(coverage)
function new(string name = "coverage",uvm_component parent);
super.new(name,parent);
cg1 = new();
endfunction : new
virtual function void build_phase(uvm_phase phase);
super.build_phase(phase);
apb_imp = new("apb_imp",this);
ahb_imp = new("ahb_imp",this);
mem_imp = new("mem_imp",this);
mem_item = mem_seq_item :: type_id :: create("mem_item");
ahb_item = ahb_m_seq_item :: type_id :: create("ahb_item");
apb_item = apb_transfer :: type_id :: create("apb_item");
endfunction : build_phase
virtual function void write_ahb(ahb_m_seq_item item);
$cast(ahb_item,item.clone());
item.print();
if(ahb_item.htrans[0] == NONSEQ)begin
in_addr = ahb_item.haddr;
end
cg1.sample();
endfunction : write_ahb
virtual function void write_apb(apb_transfer item);
apb_item = item;
if(item.paddr == 'h8)begin
l_ctrl_reg = item.pwdata;
end
else if(item.paddr == 'h0)begin
l_start_reg = item.pwdata;
end
else if(item.paddr == 'h4)begin
l_end_reg = item.pwdata;
end
cg1.sample();
endfunction : write_apb
virtual function void write_mem(mem_seq_item item);
mem_item = item;
cg1.sample();
endfunction : write_mem
endclass : coverage