Could someone tell me how to use “#xxx” to set delay time in my test?

SystemVerilog
,
1

Here is my code in testcase: (timescale 1ps/1ps) SIM TOOL: vcs

·uvm_info(“TIME”,“TP1”,UVM_LOW)
#50000;
·uvm_info(“TIME”,“TP2”,UVM_LOW)

when I use the code above , it will delay 50us in my test . that means #1 = 1ns why ? as I set the timescale is 1ps/1ps , why #1=1ns ?

Here is another code in my testcase : (timescale 1ps/1ps) SIM TOOL: vcs

·uvm_info(“TIME”,“TP1”,UVM_LOW)
#50us;
·uvm_info(“TIME”,“TP2”,UVM_LOW)

when I use #50us , it will delay 50us x1000 = 50000us ? I cant understand that , is it a bug for VCS ?

if I use #50ns instead of the #50us , it will delay 50nsx1000 = 50us that makes me very confused. VCS gose wrong ?

2

In reply to Achilles:

if you set timescale to 1ps/1ps, but still got #1=1ns in your simulation, you’d better print out timescale before you start to wait #50000 by using cmd below:
$printtimescale(path)
Generally, if have other files re-define the timescale, your wait time will be different without notifying you.
So if there are several persons working on the same environment and you only handle part of the env(especially RTL also have the right to change timescale), better define your own wait task inside tb_top where you can call in sub-file:

 
 timeunit 1ns
 timeprecision 1ps

 task dly_ns(input real delay);
    #delay;
 endtask:dly_ns
 task dly_us(input real delay);
    #(delay*1000);
 endtask:dly_us

Now you can call dly_ns(num) or dly_us(num) as you want.

3

In reply to Celine Chen:

Thanks for your help, I add these ns_task , ps_task and us_task in the tb_top , and call these task in my testcase , I get the ps ns and us delay cocrrectly.

But there is still a question I want to ask , I put “timescale 1ps/1ps” in the top of the testcase just for test ,and call the $printtimescale(path), the sim_log shows me that the timescale is still “timescale 1ns/1p”,could you tell me why ?

4

In reply to Achilles:

timescale has a property to pick whatever the latest definition is. Even if you have specified 1ps/1ps there might be submodule or tb blocks whose timescale might be different and it would be overwritten.

It is suggested to check ifdef TIMESCALE … before your task/method and update it back with the required timescale.