Convert hex string to logic

SystemVerilog
1

I am trying to find a “sane” way to converting a hex formatted string to a logic.

here is what i have tried so far and where i am stuck

My idea was to loop through the string and grab the individual bytes and convert them from ASCII to a 4 bit nibble.

something like this:

module test;
  
  initial begin
    $display("Hello World!");
    hexs_to_reg("DEADBEEF");
  end
  
  function [31:0] hexs_to_reg(string hex_string);
    logic [31:0] reg_val;
    string byte_string;
    byte byte_byte;
    for (int i=0;i < hex_string.len();i++) begin  
      byte_string =hex_string[i];
      byte_byte = byte'(byte_string.atohex());
      reg_val[4*i -: 4] = byte_byte;
    end
    return reg_val;
	endfunction
  
endmodule

However when I index through the string like this it seems that it wasnt to return a byte type…

which is fine except the atohex() function is not defiend for byte type…

i am sure i can write my own implementation for atohex()… but i am thinking i am not the first person to do this… and there is a “saner” way of doing this.

2

In reply to mreister:

You are making this more complicated than it needs to be:

module top; 
  logic [31:0] hex_to_reg;
  string s;
  initial begin
    s = "DEADBEEF";
    hex_to_reg = s.atohex();
    $display("%h", hex_to_reg);
  end
endmodule