Control over randomization without using constraint

SystemVerilog
, ,
2

In reply to araj380:


module print_0or3_only;
  int var_1;

  initial begin
    repeat(30) begin
      var_1 = 3 * $urandom_range(0,1);
      $display("\nvar_1 = %0d",var_1);
    end
  end
endmodule