Continuous vs procedural assignment

SystemVerilog
1

wire out ;
reg [2:0] current_state;

Case 1: assign out = (current_state = S3)&(in == 1’b1) ? 1’b1:1’b0;
Error: current_state is reg which is inavlid in assign

case 2: assign out = (current_state == S3)&(in == 1’b1) ? 1’b1:1’b0;
compilation passing

Why in second case reg is not taken care of ? is it taking absolute value ?

2

In reply to surajX:

A single ‘=’ is a procedural blocking assignment inside a larger expression, they are only allowed in procedural contexts.