In below code, ‘b’ to ‘a’ assignment, Never happens(tried on edaplayground) Why ?
Example values of ‘b’ w.r.t. time
// 0 to 1ns,b=0;
//1 to 3ns,b=1;
// 3 to 8ns,b=0;
// 8 to $,b=1;
module top;
logic a,b;
//assign a=b;
assign #4 a=b; // Never happens. Why ? timing regions ?
initial begin
#1 b=1;
#2 b=0;
#5 b=1;
end
endmodule
This is because continuous assignments (as well as gate-level primitives) use what is called an inertial dealy model. This means only one scheduled change can be placed on the output at a time. If the inputs change faster than the output delay, the previous change gets cancelled.
In your example, a is initially x at time 0 and first scheduled to change to 1 at time 5. Next at time 3, the change to 1 gets cancelled and replaced with a change to 0 at time 7, which does occur.
If you run the simulation long enough, you will see a changes to 1 at time 12.
