Constraints

SystemVerilog
1

Assume that you have two properties
rand bit [7:0]a;
rand bit [2:0]b;

The range of values for b are 3,4,7

If b==3, the number of ones in the binary number must be 4.
If b==4, the number of ones in the binary number must be 5.
If b==7, the number of ones in the binary number must be 8.

Write constraints for above scenario.

2

In reply to Rakesh Kumar S:
Hint: use $countones(a)

3 
module example;

class ex;
 rand bit [7:0]a;
 rand bit [2:0]b;

  constraint range {b dist {7:=2,4:=2,3:=2};}
 constraint count {$countones(a)==(b+1); }
endclass

ex ex1;
initial
 begin
  
   repeat(10)
   begin
   ex1=new();
   assert(ex1.randomize);
     $display("a=%b,b=%d",ex1.a,ex1.b);
   end
 end
endmodule