Constraints to pick an element from queue

SystemVerilog
, , ,
1

I have a static Queue in a class, and the elements of the queue are set by some module using the class name.
I am getting constraint failure when I try to pick an element from the queue.
Code -


class seq_item;
    static logic [31:0] addressQ [8][4][$];
    rand bit [31:0] addr;
    constraint pickaddr {
        <some condition> -> addr inside {addressQ[0][0]};
    };
endclass

module set_q;
    logic [2:0] i,j;
    <some combinational module sets value of i and j>
    always @(posedge clk) begin
        seq_item::addressQ[i][j].push_back(urandom());
    end
endmodule

I am getting constraint failure -
condition → 1’b0
How do I pick values from the queue in constraints

2

In reply to sandman:

That’s not enough code to show exactly what is wrong, but probably you are calling randomize() before anything gets pushed into seq_item::addressQ[0][0]. If is true, the inside operator will be false.