Constraints on memory

SystemVerilog
1

Hi,

there is a memory with 32 bit wide and depth is 64.
for first 10 locations ,out of 10 location four locations with all 1’s , 3 locations with random number, remaining three with all zeros needs to be written. remaining locations not to be randomized. Please let me know how to write system verilog constraints for that.

Thanks
Srilakshmi

1 Like
2

In reply to srbeeram:

Your requirements need some clarifications. Are all the constraints for the first 10 locations? i.e when you say remaining locations, you mean elements 10-63? If that is the case, then the following should work:

class A;
    rand bit [31:0] memory10[10];
    bit [31:0] memory[64];
    constraint c_mem {
      memory10.sum() with (int'(item == '1)) == 4; 
      memory10.sum() with (int'(item == '0)) == 3; 
    }
    function void post_randomize();
      memory[0:9] = memory10;
    endfunction
  endclass
  
  A a=new;
  
  initial repeat(4) begin
    assert(a.randomize());
    $display;
    foreach(a.memory[i]) $displayh(a.memory[i]);
  end
endmodule
3

In reply to dave_59:

Thanks Dev for providing clarifications.