Constraints for unique value in registers

SystemVerilog
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1

Hello,
I have a situation in which i am having 16 4-bit registers, each registers are randomized on the same time but they shouldnt have the same value all 16 should be different. the constraints which i think should work are not working.

constraint addr {!(reg1 inside {reg2,reg3,reg4,reg5,reg6,reg7,reg8,reg9,reg10,reg11,reg12,reg13,reg14,reg15}; }

similarly i have given for every registers.
can anyone tell me another way it may work??

Thank you

2

SystemVerilog 2012 added a unique constraint described here.

constraint addr {unique {reg1,reg2,reg3,reg4,reg5,reg6,reg7,reg8,reg9,reg10,reg11,reg12,reg13,reg14,reg15}; }

But why not use an array?