Constraint

SystemVerilog
,
11

In reply to 100rabhh:

I believe you have run into a tool bug. The following code works on 4 SystemVerilog simulation tools on www.edaplayground.com.

class my_trans;
  rand bit[31:0]  reg_a [24];
  function void post_randomize;
    foreach(reg_a[,j]) $display(reg_a.sum() with (int'(item[j])));
  endfunction
endclass
module ab;
  my_trans trans_h= new ;
  initial  assert(trans_h.randomize());
endmodule

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