Constraint with Multiple array dependencies

SystemVerilog
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1

I have two class member arrays:

rand bit [3:0] grp_depth[num_of_groups]; rand bit [15:0] sub_grp_enables[num_of_sub_groups]

now each group has all the sub_groups with randomly enabled 16bits. each bit enabled means 4Bytes of space.

Now total such size needs to be within a given size. Want these grps and subgroups and number of elements in that group to be randomly selected.

theoretical requirement expression =

for (int i=0; i<num_of_groups;i++)
  for (int j=0; j<num_of_sub_grps;j++)
    for (int k=0; k<15; k++)
      if (sub_grp_enables[j][k]==1) total_size+=grp_depth[i];

this size should be less than 512KB

So how do i write random constraint to enable this size restriction while generating grp_depth and grp_enables randomly?

I am trying to write something like this if i solve the expression taking out the common groups. But i cannot use … in the real code :(

 constraint RAM_SIZE_c {

 ($countones(sub_group[0]) + $countones(sub_group[1])+...+$countones(sub_group[`num_of_sub_groups]) )*
  (grp_depth[0]+grp_depth[1]+....+grp_depth[num_of_groups]) <= 512KB

}

Any good suggestions?

Thanks and Regards,
Lakshmi Kanth

2

In reply to lakshmikanth_t:
But you can use … using the sum() method.

 constraint RAM_SIZE_c {
         (sub_group.sum() with ($countones(item)) * grp_depth.sum() with (int'(item)) )
          <= 512KB ;}