Constraint to print pattern 122333444455555

SystemVerilog
, ,
11 
class pattern;
	rand int a[];
	constraint c2 { a.size==6;}
	constraint c1 { foreach (a[i])
			a[i]==(1*(i+1)*(10**(i+1)-1))/9;}

endclass
module m;
pattern p;
initial
begin
	p=new;
	assert(p.randomize);
	foreach(p.a[i])
	$display("pattern is %d",p.a[i]);
		end
endmodule