Constraint to generate two mutually exclusive arrays

SystemVerilog
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1

I want to write a system verilog constraint to generate two mutually exclusive arrays with random values in it. it is possible with unique keyword in the sv constraint. But i want it without unique keyword. Please share if some one found the answer… Thanks in advance :-)

2

In reply to mani90:

I think you can try something like this

rand bit[3:0] a[10];
constraint abc { foreach(a[i]) foreach(b[j]) if(i!=j) a[i] != a[j];}

This is for one arary can be done for the another array as well.

Cheers…