Constraint to generate start and end address for a memory block

SystemVerilog
, ,
1

Hi,

I want to write a constraint to generate random start and end addresses to pick a block of memory inside a particular range of addresses, and i cannot use the address range which picked previous. can you please help me to write a constraint that pick start and end addresses for 10 blocks with in 0 to 1023 address range.

method i tried :

constraint c_rand_mem_block {
  foreach(start_addr[i])
  {
    start_addr[i] inside {0:1022};
    unique{start_addr};
    // randomizing the start address and generate the end addresses with in the each start address.
  }
   
   foreach(end_addr[i])
   {
     end_addr[i] inside {start_addr[i]+1 : next_start(start_addr[i])-1};
     // here next_start is the start address followed by the current start address.
     // I am trying to keep the end address within the next start address.
   }    
}

but the issue is i am using a function to get the next_start and whenever this is called in the foreach of the end_addr the start_addr is randomizing again so, the previous start_addr values are not useful and dont match the end_addr.

Please help me to solve this issue or please tell me if there is a better way to do the same constraint

Thanks,
Jaswanth.

2

In reply to jaswanth_b:

See:

https://verificationacademy.com/forums/systemverilog/constraint-memories#reply-76718
https://verificationacademy.com/forums/uvm/constraining-address-memory-making-sure-offset-not-within-previous-memory-regions.#reply-63179

3

In reply to dave_59:

Hi Dave,

Thanks for your reply.