Constraint the 2-D array size

SystemVerilog
, , ,
2

In reply to jj_bukhari:

Please use code tags making your code easier to read. I have added them for you.

I’m not getting any errors from running your code. It would help to show a minimal complete example and the error you are getting.

This is what I tred

class child;
  rand bit[3:0] dy_array[][]; //2-D dynamic array
  constraint arr_size_limit{dy_array.size inside{[1:4]}; foreach(dy_array[i]) (dy_array[i].size==2); } //constraint to limit the dy_array size  
endclass:child
module top;  
  child c = new;
  initial repeat (5) begin
    assert(c.randomize);
    $displayh("%p", c.dy_array);
  end
endmodule

and the results I got

# '{'{a, 6}, '{5, e}, '{7, 7}}
# '{'{e, 4}, '{3, f}, '{d, 4}, '{3, b}}
# '{'{f, a}}
# '{'{5, 0}}
# '{'{1, 5}, '{5, 1}, '{6, f}, '{4, 0}}