Constraint randomization of an array

SystemVerilog
17

In reply to gnich:

In reply to dave_59:
I was able to get this working using int’(item) when using Cadence.

class rand_vf_queues extends uvm_object;
rand bit [7:0]  vf_size;
rand bit [11:0] vf[];
rand int queues;
constraint c_num_vf      {vf_size == 248;}
constraint c_num_queues  {queues == 2048;} 
constraint c_vf_queues {
vf.size == vf_size;
vf.sum with (int'(item)) == queues;
foreach (vf[i]) {
vf[i] inside {[0:queues]};
}
}
function new (string name = "");
endfunction // new
endclass

Hi,

In Cadence tool I am getting the following output with the below code:
B2B_seq_array[0] === 1712505664
B2B_seq_array[1] === 1648995472
B2B_seq_array[2] === 1324445776
B2B_seq_array[3] === 3903987720

Code:

module tb;

class muneeb;
   
  rand int unsigned B2B_seq_array[];

    
  constraint sum_c { B2B_seq_array.sum with (int'(item)) ==40;}
  // I even tried the below constraint but still no sucess
  // constraint sum_c { B2B_seq_array.sum() with (32'(item)) == 40;}

  constraint b2b_array_c { B2B_seq_array.size() == 4; }
  
  constraint mm_c {              foreach(B2B_seq_array[i]) {
                                 (B2B_seq_array[i] % 8) == 0;   
                                 B2B_seq_array[i] != 0;   						
                          }
  
    }
    
endclass


  muneeb m1;

  initial
  begin
  m1 = new();
    if(!m1.randomize())
      $display("Randomizeation failed");
    else
        begin
          foreach(m1.B2B_seq_array[i])
            begin
            $display("B2B_seq_array[%0d]  === %0d",i,m1.B2B_seq_array[i]);
            end
        end
  end
endmodule

Can you please help me with this regard.

Thank you,

Regards,
Muneeb