Constraint randomization of an array

SystemVerilog
16

In reply to dave_59:

I was able to get this working using int’(item) when using Cadence.

class rand_vf_queues extends uvm_object;

   rand bit [7:0]  vf_size;
   rand bit [11:0] vf[];
   rand int queues;
   
   constraint c_num_vf      {vf_size == 248;}
   constraint c_num_queues  {queues == 2048;} 

   constraint c_vf_queues {
			 vf.size == vf_size;
			 vf.sum with (int'(item)) == queues;
                         foreach (vf[i]) {
			   vf[i] inside {[0:queues]};
                         }
                        
   }

 
   function new (string name = "");
   endfunction // new

endclass