Constraint Randomization Interview Question

SystemVerilog
4

In reply to ABD_91:
Good solution, thank you.
Added an assertion


module m; 
  c c1=new(); 
  initial begin 
    repeat(15) begin
      if (!randomize(c1)) $display(" XXX FAILS !! XXX ");
      $display("c1.v= %b", c1.v);
      ai_12: assert($countones(c1.v)==22) 
      else  $display("ERROR c1.v1= %b, countones= %d", c1.v, $countones(c1.v));
    end
  end
endmodule
// simulation 

#  int1  is  1 , int2 is 10
# c1.v= 11111111111111111111100000000001
#  int1  is  8 , int2 is 17
# c1.v= 11111111111111000000000011111111
#  int1  is  16 , int2 is 25
# c1.v= 11111100000000001111111111111111
#  int1  is  15 , int2 is 24
# c1.v= 11111110000000000111111111111111
#  int1  is  1 , int2 is 10
# c1.v= 11111111111111111111100000000001
#  int1  is  17 , int2 is 26
# c1.v= 11111000000000011111111111111111
#  int1  is  22 , int2 is 31
# c1.v= 00000000001111111111111111111111
#  int1  is  15 , int2 is 24
# c1.v= 11111110000000000111111111111111
#  int1  is  11 , int2 is 20
# c1.v= 11111111111000000000011111111111
#  int1  is  10 , int2 is 19
# c1.v= 11111111111100000000001111111111
#  int1  is  22 , int2 is 31
# c1.v= 00000000001111111111111111111111
#  int1  is  3 , int2 is 12
# c1.v= 11111111111111111110000000000111
#  int1  is  22 , int2 is 31
# c1.v= 00000000001111111111111111111111
#  int1  is  14 , int2 is 23
# c1.v= 11111111000000000011111111111111
#  int1  is  20 , int2 is 29
# c1.v= 11000000000011111111111111111111