Constraint Randomization Interview Question

SystemVerilog
3

In reply to Ammu786:


class c; 
  
  rand bit[31:0] v;  
  
  rand int int1 , int2 ;
  
  constraint  LOW_BOUND     {  int1  inside { [ 0 : 31 ] } ; }
  
  constraint  UPPER_BOUND   {  int2  inside { [ 0 : 31 ] } ; }
  
  constraint  DIFF          {  int2 ==  int1  +  9 ;  }  // Range of  Indexes  is  10  !!
  
  // constraint ct12 { $countones(v) == ( 32 - 10 ) ; }  // Can be Skipped  !!
  
  constraint  VAL  {     foreach( v[i] )
                        {   
                          if( i inside { [ int1 : int2 ] } ) 
                            v[ i ] == 0 ;
                          else
                            v[ i ] == 1 ;
                        }
                   }
  
    function  void  post_randomize() ;
    $display(" int1  is  %0d , int2 is %0d" , int1 , int2) ;
    endfunction
                    
endclass 
 
module m; 
    c c1=new(); 
 
  initial begin 
    repeat(5) begin
      if (! c1.randomize() ) $display(" XXX FAILS !! XXX ");
      $display("c1.v= %b", c1.v);
      
    end
  end
endmodule
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