In reply to Ammu786:
Not what you asked, working on the continuous 10 bits a
class c;
rand bit[31:0] v;
constraint ct12 {$countones(v)==12;}
// $countones (expression) returns the number of ONEs in a bit vector expression.
endclass
module m;
c c1=new();
initial begin
repeat(5) begin
if (!randomize(c1)) $error();
$display("c1.v= %b", c1.v);
ai_12: assert($countones(c1.v)==12)
else $display("ERROR c1.v= %b, countones= %d", c1.v, $countones(c1.v));
end
end
endmodule
/* sim results
# c1.v= 01010001000101000100110010001011
# c1.v= 01000100001110000101100011010001
# c1.v= 00111111010000001010001000010100
# c1.v= 10100110100100100001010001100100
# c1.v= 01001110100000101011010000100100 */
Ben Cohen
http://www.systemverilog.us/ ben@systemverilog.us
** SVA Handbook 4th Edition, 2016 ISBN 978-1518681448
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