Constraint: Random variable shows up as a constant in solver

SystemVerilog
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2

In reply to Prathamesh Shinde:

Using if/else in a constraint is effectively two implications.

srfc_type inside {1, 4} -> route_to_l1 == 1;
!(srfc_type inside {1, 4}) -> route_to_l1 == 0;

Since you are constraining
srfc_type to be 0 using the with clause, then
route_to_l1 must also be 0 according to the second implication.