Constraint on even and odd number

SystemVerilog
,
1

hi, can some one tell me. how to write a constraint for below question.

I have an array with size 100.
now I want values which are dependent on my odd and even indexes of array.

  1. for array[odd numbers]= even numbers should be assigned.
  2. for array[even numbers]= odd numbers should be assigned.
2

In reply to subbarao:



class transaction;

rand bit[15:0]array[100];

constraint C1 { foreach(array[i])
                    if(i%2==0)
                          array[i]%2 !=0;
                    else
                         array[i]%2 ==0;}
endclass
3

In reply to subbarao:

foreach (q[i]) {
(i%2) != (q[i]%2);
}