CONSTRAINT ON AN ARRAY WITH SET BITS

SystemVerilog
, , ,
2

In reply to prashantk:


rand bit [15:0] available;
rand bit [3:0]  choose;

constraint c {
   foreach(available[i])
      (available[i] == 0) -> (choose != i);
   solve available before choose;
}

// alternative way, not sure if it compiles lol
constraint b {
   available[choose] == 1;
   solve available before choose;
}

// same, I prefer this one, ha
constraint a {
   available | (1 << choose) == available;
   solve available before choose;
}