Constraint of address in higher limit and lower limit and some of the adress in between

SystemVerilog
,
1

Hi

I have a scenario which includes following Constraint to be taken care :: Please help on the logic

1)There is a 2MB memory address, i have to constraint the address in such a way that every time the test executes it hits the higher limit
and the lower limit and some of the address in between the space.

  1. I have to covert the byte variable in to Dword size, is there a inbuilt SV function to do it? or easy way ?

Thanks

2

In reply to syed taahir ahmed:

There are many ways to do this if you give more details. For example, you could write a directed test

randomize () with {address == low_limit};
...
randomize () with {address inside ([low_limit+1:high_limit-1]};
...
randomize () with {address == high_limit};

You could also use the ‘list’ constraint if you call randomize enough time to have a high probability of hitting the limits.

randomize() with {address dist {low_limit:=1, high_limit :=1, [low_limit+1:high_limit-1] :=1};}

You second question needs an example and should be a separate post

3

In reply to dave_59:

In reply to syed taahir ahmed:
There are many ways to do this if you give more details. For example, you could write a directed test

randomize () with {address == low_limit};
...
randomize () with {address inside ([low_limit+1:high_limit-1]};
...
randomize () with {address == high_limit};

You could also use the ‘list’ constraint if you call randomize enough time to have a high probability of hitting the limits.

randomize() with {address dist {low_limit:=1, high_limit :=1, [low_limit+1:high_limit-1] :=1};}

You second question needs an example and should be a separate post

Ok Dave, I will use another post for second question .

But for your question-1, the solution works.