Constraint is not working

SystemVerilog
, ,
1

I had written constraint for 6 varibles but its not working so can anyone please guide me where i am lacking?

Requirement is :

a,b,c between 0 to 7 but b != a and c != b or a
x,y,z between 0 to 63 but y != x and z != x or y

class error_constraint;
  rand int a,b,c,x,y,z;
  constraint a1 { a inside { [00:07] }; }
  constraint a2 { (b != a) -> b inside { [00:07] }; }
  constraint a3 { (c != a | c != b) -> c inside { [00:07] }; }
  constraint x1 { x inside { [00:63] }; }
  constraint x2 { (y != x) -> y inside { [00:63] }; }
  constraint x3 { (z != x | z != y) -> z inside { [00:63] }; }
endclass

module a;
  error_constraint err = new();
  initial begin
  repeat(10)
    begin
      void'(err.randomize());
      $display("%0d %0d %0d %0d %0d %0d",err.a,err.b,err.c,err.x,err.y,err.z);
    end
  end
endmodule
2

In reply to om30:

You need to explain the “but” operator in your description. I think you mean

a,b,c has a value between 0 to 7, additionally a,b,c must have unique values. The constraint would look like:

constraint a1 { a inside { [00:07] }; }
constraint b1 { b inside { [00:07] }; }
constraint c1 { c inside { [00:07] }; }
constraint.u1 { unique {a,b,c}; }
3

In reply to dave_59:

Thank You Sir,
Got it!