Constraint Interview Question

SystemVerilog
,
1

A colleague and I were discussing an interview question .


  class  Base ;
  
    rand  bit  [ 7:0]  b ;

    constraint  VAL  {  b < 10 ; } 
 
  endclass

   class  Ext  extends  Base ;
     ....................
   endclass

If the base class is treated as a black box where even the constraint isn’t visible .

Is there a way to constraint it the opposite way from extended class ( i.e b > 10 ) from extended class ?

2

In reply to Have_A_Doubt:

The only way of removing a constraint in a base class is by turning it off with constraint_mode() or overriding it using an extended class. There is no way to accomplish either without knowing the name of the constraint in the base class. If the author of the base class hides that information, they likely had a reason for not wanting you to know about it, and thus modifying it.

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