Constraint for unique address ranges

SystemVerilog
,
1

Hello I want to constraint address ranges for my transactions, but it doesn’t occur to me how to do it in the best way.
It’s write transaction that have start address, but can send up to 512 bytes, so it takes some range of addresses.
But the basic idea is as follows:

  1. Take start address from range [0:7F_FFF]; (pretty easy)
  2. Write transaction can be [4:512] bytes, so 1 transaction in reality takes range from addrsss field [1200:13ff] for example. (so we need save not only start address but address + size?)
  3. I want to save that ranges and when start next transaction it must check and avoid any intersection between previous used ranges and create a unique new one range transaction with random size and start address.

I have experience in creating this kind of constrain for single addresses and saving them to an associative array in post_randomize.

May be some one have experience with address ranges too?

2

In reply to defmaxou:

class abc;
  rand bit [18:0] start_addr;
  rand bit [9:0] data_size;
  rand bit [18:0] end_addr;
  bit [18:0] st_addr[];
  bit [18:0] en_addr[];
  int i;
  constraint data_c  { data_size inside {[4:512]};}
  constraint addr_c  { end_addr == (start_addr+data_size-1);}
  constraint st_addr_c { foreach(st_addr[j])
    !(start_addr inside {[st_addr[j]:en_addr[j]]});
                     }
  
  function void post_randomize();
    st_addr= new[st_addr.size()+1](st_addr);
    en_addr= new[en_addr.size()+1](en_addr);
    
    st_addr[i]=start_addr;
    en_addr[i]=end_addr;
    i++;
  endfunction
  
endclass

module top;
  abc a1;
  
  initial begin
    a1=new();
    repeat(5) begin
      assert(a1.randomize());
      $display("%p",a1);
    end
  end
endmodule

Thanks,
Juhi Patel
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