Constraint for selecting multiple byte lanes

SystemVerilog
, ,
3

In reply to dave_59:

Thanks for your comment and code.

Please refer my code…

In my case, I describe constraints to `uvm_rand_send_with.
I try to refer your code. The ‘size’ and ‘array’ are declare in the ‘tr’ class. But ‘helper’ isn’t declare in the class.
I want to use ‘helper’ as local rand variable in the ‘seq’ class even though I can declare a variable like ‘helper’ in the ‘tr’ class.
Can I use a ‘helper’ variable in the ‘seq’ class?

My code is below.


class seq;

  tr tr_obj;

  task body ();
    `uvm_create(tr_obj);
    
    ...
    
    `uvm_rand_send_width(tr_obj, {
      // constraint for selecting byte lane
    }
  endtask

endclass

class tr;
  rand logic [2:0] size;
  rand logic [31:0] array[];
endclass

I trying like below. This code doesn’t work. I trying to fix it.


class seq;

  tr tr_obj;

  rand helper[];

  task body ();
    `uvm_create(tr_obj);
    
    ...
    
    `uvm_rand_send_width(tr_obj, {
      local::helper.size() inside {1,2,3,4,5,6,7,8};

      tr_obj.array.size() == tr_obj.size;
      foreach ( local::helper[select_lane] ) {
        foreach ( tr_obj.array[i] ) {
          tr_obj[i][(select_lane)*4+;4] inside {'0, '1};
        }
      }
    }
  endtask

endclass

class tr;
  rand logic [2:0] size;
  rand logic [31:0] array[];
endclass