Constraint for selecting multiple byte lanes

SystemVerilog
, ,
2

In reply to jh_veryveri:

This can be done using a helper array (an array used to make constraints easier to write). In this case, the helper lets you iterate over each byte lane.

module top;
  class my_class;
    rand logic [2:0] size;
    rand logic [31:0] array[];
    rand bit helper[8];
    constraint c {
      array.size() == size;
      foreach(helper[lane]) {
        helper[lane] == lane < size;
        foreach(array[i])
          if (helper[lane])
            array[i][lane*4+:4] inside {'0,'1};
          else
            array[i][lane*4+:4] == '0;
      }
    }
  endclass
        
  my_class c = new;
      initial repeat(5) begin
        assert(c.randomize() );
    $displayh("%p %p",c.array,c.helper);
  end
endmodule