Constraint for a value range not inside a value range

SystemVerilog
5

In reply to dave_59:

Thanks Dave for the solution.

I modified the code a bit.

module top();

bit [7:0] range_of_values[$];

class packet;
   rand bit [7:0] a;
   rand bit [2:0] s;
 
   function void post_randomize;
      for(int ii=a; ii<=a+s; ii++)
	range_of_values.push_back(ii);
   endfunction

   constraint no_overflow { 8'(a+s) == int'(a+s);}
 
endclass : packet

initial
begin
  packet pp;
  pp = new();
  pp.randomize() with { // pp.a != 5 &&
                        foreach(range_of_values[ii])
                              !(range_of_values[ii] inside {[a:a+s]});
                      };
end

endmodule

The above code works.

If I uncomment the part “pp.a !=5 &&” I see compile error

** Error: (vlog-13069) aa.sv(23): near “foreach”: syntax error, unexpected foreach.

Let me know how to avoid it.

Sunil.