Constraint for a value range not inside a value range

SystemVerilog
4

In reply to KumarSunilB:

Thanks, that is very clear now. Try this:

class packet;
   rand bit [7:0] a;
   rand bit [2:0] s;
   bit [7:0] range_of_values[$];

   function void post_randomize;
      for(int ii=a; ii<=a+s; ii++)
	range_of_values.push_back(ii);
   endfunction
   constraint not_in_range {
			    foreach(range_of_values[ii])
			    !(range_of_values[ii] inside {[a:a+s]});}
   constraint no_overflow { 8'(a+s) == int'(a+s);}
   
endclass : packet