Constraint a 9x9 matrix

SystemVerilog
,
6

In reply to UVM_SV_101:

module test;

class pixel;
rand bit a[9][9];

constraint abc { foreach(a[i,j])
		  a[i][j]==0 dist {0:=71 ,1:=10};}

endclass

pixel pic;

initial
begin
pic=new;

void'(pic.randomize);
$display("%p",pic);
end
endmodule