Constraining sum() of diagonal elements to 1

SystemVerilog
,
1

I have 2D unpacked array :


class A;

rand bit arr [8][8];

    // Absolute value                                                                                                                                                                        
    function int abs(int val);                                                                                                                                                               
      return val >=0 ? val : -(val);                                                                                                                                                       
    endfunction 
 
constraint UNIQ_ROW {
                      foreach( arr[i] )
                       arr[i].sum() with ( int'( item ) )  == 1 ; 
		    }

               // column sum == 1                                                                                                                                                                       
constraint col  {                                                                                                                                                                                                                                                                                                                                                                
		   foreach (arr[r1,c1]) 
                      foreach(arr[r2,c2])                                                                                                                                             
		    {                                                                                                                                                                                
		      ( (c1 == c2) && (r1 != r2) && arr[r1][c1]==1 ) -> ( arr[r2][c2] == 0 );                                                                                                                
		    }                                                                                                                                                                                
		}   
              
constraint diag {     foreach (arr[r1,c1]) foreach (arr[r2,c2])                                                                                                                                                                     		                                                                                                                                                                                                                                                                                                                                   
		      {                                                                                                                                                                                
		    ( ( abs(r1-r2) == abs(c2-c1) ) && r1!=r2 && c1!=c2 && arr[r1][c1]==1 ) -> ( arr[r2][c2] == 0 ) ;                                                                                          
		      }                                                                                                                                                                                
		}

The diagonal constraint ensures that if an element is 1 , all it’s respective diagonal elements would be 0

My question is whether there is an alternative to diagonal constraint using array reduction method : sum() ?

2

In reply to ABD_91:

You just missed this:

https://verificationacademy.com/forums/systemverilog/n-queen-board-problem-sv-constraint#reply-114849