Constraining OCM base addresses

SystemVerilog
,
1

Hi Forum,
I have two 64-bit variables ( tc_baddr & mapr_baddr ) which are used as AwAddr by the DUT.
DUT has 6K deep FIFO where it holds data for both TC IP & Mapr IP.
Suppose DUT sends 6k Wdata for either of the 2 IPs with ‘mapr_baddr’ / ‘tc_baddr’ as 64’d0.
DUT sends 1st Wdata at AwAddr 64’d0 , 2nd Wdata at AwAddr: 64’d8 , … ,
6143th Wdata at AwAddr: 64’d49,144
DUT essentially has the following code ::

// Due to 6K FIFO , ocm_tail_ptr goes from 0 to 6143
awaddr = is_tc ? ( tc_baddr + ( ocm_tail_ptr << 3 ) ) : ( mapr_baddr + ( ocm_tail_ptr << 3 ) );

I want to constraint these 2 base addresses such that ::

(1) Both are different i.e tc_baddr != mapr_baddr ;

(2) Both are byte addressable i.e tc_baddr[2:0] == 0 ; mapr_baddr[2:0] == 0 ;

(3) In a scenario where DUT sends 64K Wdata only for one of the 2 IPs ( starting from their base address ) it shouldn’t cross 64K

    i.e  tc_baddr + 'd49_144 <= 64'hFFFF_FFF8 ;  // When tc_addr > mapr_baddr
    i.e  mapr_baddr + 'd49_144 <= 64'hFFFF_FFF8 ;  // When mapr_addr > tc_baddr

(4) There should be min. difference of 'd49,152 between the 2 base addresses so that AwAddr doesn’t overlap ( else Tb won’t be able to differentiate whether the Wdata is for TC or Mapr IP )

Here is my attempt

bit[63:0] tc_baddr , mapr_baddr;
if( !std::randomize(tc_baddr,mapr_baddr) with { tc_baddr != mapr_baddr ;
                                               tc_baddr[2:0] == 0 ; mapr_baddr[2:0] == 0;
                                               if( tc_baddr > mapr_baddr )
                                              {   // 70' cast to avoid overflow
                                                70'(tc_baddr) >= 70'( mapr_baddr ) + 'd49_152;
                                                70'(tc_baddr) + 'd49_144 <= 64'hFFFF_FFF8;
                                               } 
                                              else 
                                              {  // 70' cast to avoid overflow
                                                70'(mapr_baddr) >= 70'( tc_baddr ) + 'd49_152;
                                                70'(mapr_baddr) + 'd49_144 <= 64'hFFFF_FFF8;
                                               } 
                                          }  ) `uvm_error(get_type_name(),"Randomization Failed")

I have the following knowledge on constraint solver ::
(a) All hard constraints have equal priority & are solved in parallel
(b) solve before is poorly named in LRM as the variables are all chosen together i.e out of the solution space that satisfies all the constraints, any of values are picked

I am not clear on how the if-else works as by then wouldn’t the constraint solver have picked a value for ‘tc_baddr’ & ‘mapr_baddr’

2

Although if/else in a constraint looks like procedural code, it is just an expression.

constraint c{ if(A) B else C;}

is the same as

constraint c{ A && B || !A && C}

Note that B and C can both be true. But in your example, I think the use of relational operators prevent that from happening. If needed, you would use solve A before B,C to make sure A is evenly balanced in true/false cases. The if/else does not imply that.