Constraining an array of boolean values

SystemVerilog
, ,
1

The base class contains the following:-

rand boolean_e foo[8];
constraint good_foo_c {
soft (foreach[i]) {
foo[i] == TRUE;
}
}

The default constraint is that every element of foo is TRUE.
How do I relax this constraint in a derived class so that 1 or more elements of foo is/are FALSE?
Will this work?

constraint invalid_foo_c {
soft foo.sum() < 8;
}

2

In reply to new_to_uvm:

Without seeing the declaration of boolean_e, I can’t (and neither should anyone) rely on the encoding of TRUE to be 1. Also, the return type of the sum() method is by default, the same type as each element. The type when adding enums is the base integral type of the enum, which is an int, and assigning an int to an enum type is not legal without an explicit cast. So you need to use the with clause of the sum method to cast each element type.

constraint invalid_foo_c {
soft foo.sum(item) with {int'(item == TRUE)} < 8;
}
3

In reply to dave_59:

Thank You!