Constraining an array in System Verilog

SystemVerilog
1

I have a data, data[0] =header, data [1] to data[length+1] = payload, data[length +2] = parity;
header = address + length
address = 2 bit field
length = 6 bit field (decides the payload size)
Constraint has to be added for address and length
This is the problem statement
I have declared bit [7:0] data[*];
for payload i have written a constraint like , constraint payload_length {data.size inside {[1:63]};}
Now, how do i constraint the address. Requesting some suggestions.

2

In reply to Nithya_Jeevanantham:

Hi. I Went through your question. I think you are missing out on something. Minimum value of Data-size cannot be 1 because data[length + 2] = parity and (Length)min is 0. So data-size will be inside {[2:63]} . And here you have declared an associative array which is quite difficult to use in randomization. So go with the dynamic array.
Considering this one, the expected solution can be formulated like this -


class check;
  rand bit[1:0] address;
  rand bit[5:0] length;
  bit[7:0] data[];
  int header,payload,parity;
  constraint condition1{address >= 0;}
  constraint condition2{length != 0;}

  function void post_randomize();
    header = {length,address};
    for(int i=0;i<=int`(length)+2;i++) begin
      if(i==0)
        data[i]=header;
      else if(i>=1 && i<=int`(length)+1)
        data[i]=payload;
      else
        data[i]=parity;
    end
    $display("%0p",data);
  endfunction
endclass:endcheck

module doubt;
  check c1=new;
  initial begin
    c1.payload = 31;
    c1.parity = 13;
    c1.randomize();
  end
endmodule