Constraining an array field

SystemVerilog
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1

I have config object class and that class gets instantiated in other config object class as rand. I need help writing constraint for it

class  nome_mac_enet_config extends uvm_object;
   rand bit [2:0] port_lpbk_src;
 rand bit [3:0] a;

endclass

class nome_mac_config extends nome_base_config;
      rand nome_mac_enet_config enet_config[8];

constrain — I want constrain here such that each value inside enet_config[i].port_lpbk_src should be different from other… Example …
enet_config[0].port_lpbk should not be equal to enet_config[1/2/3/4/5/6/7].port_lpbk Also lets say if enet_config[4].port_lpbk= 3 then enet_config[3].port_lpbk =4 ( it should be reciprocated)

endclass

Can someone help in implementing this constraint

2

In reply to manav33:

Unfortunately you cannot use a unique constraint. You will have to use a nested foreach.

constraint c {
foreach (enet_config[i]) 
  foreach (enet_config[j]) i != j -> enet_config[i].port_lpbk_src != enet_config[j].port_lpbk_src;
}