Constrain sum of elements in an array

In reply to jtian:

No one should be using the SystemVerilog 3.1a LRM. It was released over 15 years ago before anyone had implemented anything in the specification.

See Get Ready for SystemVerilog 2012 - Verification Horizons

and Get your free copy of the IEEE 1800-2023 SystemVerilog LRM - Verification Horizons