Constrain sum of elements in an array

SystemVerilog
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8

In reply to Tudor Timi:

In reply to georgean:
Your code worked on EDAPlayground on VCS. You should contact your tool vendor.
P.S. You could have also used unique for your uniqueness constraint:


constraint data_unique_c {
unique { data };
}

Hi Timi:

I have used the unique constraint as your advice
but I got error log as blow：
*System verilog keyword ‘unique’ is not expected to be used in this context.
*

And I check the [SystemVerilog 3.1a
Language Reference Manual] , did not find discription about this.

Could you tell me where I can get any more detail about this unique constraint?

Thank you in advance.

class ttt ;
    rand bit[2:0] ddd ;
    rand bit[3:0] SA[10] ;

    constraint data_sum_c{
    SA.sum() >20;
    }
    constraint data_unique_c {
    unique { SA };
    }
endclass


module  test() ;
reg[31:0] mmm[3:0]  ;
ttt ttt_u ;

initial begin

    foreach (mmm[i]) mmm[i] = 0 ;
    ttt_u = new() ;

    ttt_u.randomize() ;
    foreach ( ttt_u.SA[i] )
    $display(" SA[%0d] = %0d", i, ttt_u.SA[i] ) ;
end
endmodule