Constrain random variable result to enumerated type

SystemVerilog
, ,
3

Added the constraint

constraint ct_inst { set==SET1 -> inst inside {[0:2]}; 
	                 set==SET2 -> inst inside {[34:36]};
	                 set==SET3 -> inst inside {[114:116]};}

Also

if(!my_class.randomize()) $error;  // <-- Use this 
      // my_class.randomize();  // Instead of this

Results

run -all;
# KERNEL: '{set:SET2, inst:34}
# KERNEL: '{set:SET2, inst:34}
# KERNEL: '{set:SET1, inst:1}
# KERNEL: '{set:SET2, inst:36}
# KERNEL: '{set:SET1, inst:2}
# KERNEL: '{set:SET3, inst:115}
# KERNEL: '{set:SET3, inst:114}
# KERNEL: '{set:SET3, inst:115}
# KERNEL: '{set:SET1, inst:1}
# KERNEL: '{set:SET1, inst:2}

Ben Cohen http://SystemVerilog.us

typedef enum bit [3:0] { SET1, SET2, SET3 } e_sets ;

typedef enum bit [7:0] { FLEE=  0, JUMP=   1, FLY=     2 } e_set1_instructions ;
typedef enum bit [7:0] { GROW= 34, SLEEP= 35, AWAKEN= 36 } e_set2_instructions ;
typedef enum bit [7:0] { RUSH=114, STARE=115, WAIT=  116 } e_set3_instructions ;

class a_class;

  // command word
  rand e_sets      set; 
  rand bit [7:0]  inst;   

constraint order { solve set before inst;} 
  
  // I need a constraint to force inst into a list defined by either
  // e_set1_instructions, e_set2_instructions, or e_set3_instructions???
  
constraint ct_inst { set==SET1 -> inst inside {[0:2]}; 
	                 set==SET2 -> inst inside {[34:36]};
	                 set==SET3 -> inst inside {[114:116]};}

endclass

// ---------------------------------------------------------------------------
module top;
  
  a_class my_class=new();
  
  initial begin
    
    for (int i=0;i<10;i++) begin
    	if(!my_class.randomize()) $error;  // <-- Use this 
      // my_class.randomize();  // Instead of this 
      $display("%p", my_class);
    end
    
  end
  
endmodule