Constrain block to allocate dedicated non over-lapping address range space for 16 masters

SystemVerilog
,
3

In reply to sruthikrapa:
For master to generate the different 4k address based on its Master number. You should use rand as variable instead of randc. You should also make sure that master address is aligned to its access boundary . In the below code its aligned 4 bytes boundary. You can change to your requirement. For 4K address space you ll need at least 12 bits.



class address;
  rand bit [15:0] addr;
  rand bit [3:0] N;
  
  constraint c_addr {
    (N ==0) -> (addr inside {[0:'h1000]} ) ;
    (N ==1) -> (addr inside {['h1001:'h2000]} );
    (N ==2) -> (addr inside {['h2001:'h3000]} );
    (N ==3) -> (addr inside {['h3001:'h4000]} );
    (N ==4) -> (addr inside {['h4001:'h5000]} );
    (N ==5) -> (addr inside {['h5001:'h6000]} );
    (N ==6) -> (addr inside {['h6001:'h7000]} );
    (N ==7) -> (addr inside {['h7001:'h8000]} );
    (N ==8) -> (addr inside {['h8001:'h9000]} );
    (N ==9) -> (addr inside {['h9001:'ha000]} );
    (N ==10) -> (addr inside {['ha001:'hb000]} );
    (N ==11) -> (addr inside {['hb001:'hc000]} );
    (N ==12) -> (addr inside {['hc001:'hd000]} );
    (N ==13) -> (addr inside {['hd001:'he000]} );
    (N ==14) -> (addr inside {['he001:'hf000]} );
    (N ==15) -> (addr inside {['hf001:'h10000]} );
    
    solve N before addr ;

  }
  
  constraint c_addr_aligned {
    addr%4 == 0 ;
  }
  
endclass
 
 
module allocation;
    initial begin
       address addr_handle;
       addr_handle = new();
 
      repeat(16) begin
        addr_handle.randomize();        
        $display("\t %4h address allocated for %0d master", addr_handle.addr, addr_handle.N);
        end
    end
endmodule