Const variable assignment

SystemVerilog
,
1

Hi All,
According to systemverilog LRM,
An Instance constants do not include an initial value in their declaration, only the const qualifier. This type of constant can be assigned a value at run-time, but the assignment can only be done once in the corresponding class constructor.

class A ; 
const int i  ;
function new(); 
i = 20;
i++;
i = 40;
endfunction
endclass

In the above case , assignments to the constant variable is done more than one time and I am getting final output i=40 (questasim), which is wrong as per LRM.
Please clarify, if I have missed something .

Regards,
Abhijeet

2

In reply to abhijeet Sahoo:

Would you please provide a reference from SV LRM for “This type of constant can be assigned a value at run-time, but the assignment can only be done once in the corresponding class constructor”.

3

In reply to prashant.kaushik:

It seems me Questa is upgraded. I tried with questa 10.4 and do not get error.

However, tried in edaplay ground and VCS is throwing compilation error for ‘re initialization’ of ‘const’ class property.

4

In reply to prashant.kaushik:

In reply to abhijeet Sahoo:
Would you please provide a reference from SV LRM for “This type of constant can be assigned a value at run-time, but the assignment can only be done once in the corresponding class constructor”.

Section 8.19 Constant class properties of the 1800-2012 LRM