Connectivity_testbench_dut

SystemVerilog
,
1

Hi All,

Please advice the following;

/////// RTL/////////

module rtl_block();

input logic rtl_in1;
output logic rtl_out1;

.....

endmodule


/////// INTRFACE/////////

interface example_intf;

logic intf_in1;
logic [4-1:0] int_out1;

endinterface


/////// TOP MODULE /////////
module top_tb;

logic tb_in1;
logic [4-1:0] tb_out1; //line1

example_intf i_intf[4] (..clk, ..rst ...);


assign tb_out1[0] = i_intf[0].int_out1;  //line2
assign tb_out1[1] = i_intf[1].int_out1;
assign tb_out1[2] = i_intf[2].int_out1;
assign tb_out1[3] = i_intf[3].int_out1;


rtl_block  instance_rtl_block(
           .rtl_in1(tb_in1),
           .rtl_out1(tb_out1), //line3

endmodule

////////////////////////////////////
Result:
code works fine for input connection. But it is giving error at line3, that is for output connection;
“Illegal combination of drivers”.
I changed at line1, from logic to wire, error fixed but not able to see the value at the interface. How can I fix this so that I should be able to see the value from both top module and interface level.
Also, tried at line2 by changing from assign to force, but received syntax error.

Regards,
Mahesh

2

In reply to Mahesh K:

  1. You have the LHS and RHS of your assign statements reversed
  2. Your rtf_out1 is only one bit wide
3

In reply to dave_59:

Dave,

1 )Means, can I not use “assign” when both the data types are logic ?
2) Yes, rtl_out1 is one bide wide, I am trying to connect to several index’s.