Connectivity checking

SystemVerilog
1

Hi,

In my SV Vector, I was trying to check an internal point to PAD connectivity as follows:-

force CHIP_TOP.PAD= 1; if (INSIDE_PHY.POINT!== 1) $display(“ERROR: PAD NOT MAPPED CORRECTLY”);
release `DUT_HIER.PAD ;

force DUT_HIER.PAD = 0; if (INSIDE_PHY.POINT !== 0) $display(“ERROR: PAD NOT MAPPED CORRECTLY”);
release `DUT_HIER.PAD ;

Now, in the Vector the 2nd check (==0) is Failing. However, in the design its connected properly. When I checked the waveform, I am not even seeing the toggle!

Qn:- Do I have to add a slight delay in between the two forces to capture the value change. If so, why? (I am trying to understand in terms of simulator / dumping behaviour; few similar checks coded in the same way was working fine. Even if the dump cannot show value change as its at same point of time, atleast the simulator shouldn’t flag en error for the 2nd check as it executes sequentially. Please correct if wrong)

Thanks in advance,
SV_Baby

2

Most simulators do not record all 0-delay glitches by default; it can be very expensive. Search your documentation in the signal dumping sections for “preserve event order” or “expand delta time” for options to change that.

When you change a signal in 0 time, the value of that signal may not always propagate, even with no delays in its path.

3

Thanks for the clarification, Dave

4

Why not use SVA for it?

a_PAD : assert #0 (`DUT_HIER.PAD ==`INSIDE_PHY.POINT) else `uvm_error ("SVA", "Mismatch");

There have been successful attempts to formally verify such issues, see:

http://bit.ly/JL9x30
http://www.facweb.iitkgp.ernet.in/~pallab/mitra_Tut3_v3.pdf

HTH
Ajeetha, CVC