connections of packages in sv design

SystemVerilog
1 
input hl_common_pkg::router_signals [1:0]  lbw_rd_rq_struct;

assume i am declaring the above signal in my rtl and below is the definition of the package.

    struct            packed {
	   logic [40:0]    payload;
	   [4:0]                  ch_header;
	}router_signals ;

so considering above declarations, can i assign like below for the connections(driving values form my testbench)…?

assign dut.lbw_rd_rq_struct.payload[4] = 1'b1;
assign dut.lbw_rd_rq_struct.payload[5] = 1'b0;

and so on.. 
can we assing individually like this..?

as i got below errors:

**Error-[PC_VIPCBD] Variable input ports cannot be driven**
**  Variable input ports cannot be driven**
2

The code you wrote should not have produced that error assuming you meant to declare ch_header with a logic datatype. input ports declared with a 4-state packed logic type are implicitly wire signals, not variables. That is a tool issue. You could declare it explicitly with

input wire hl_common_pkg::router_signals [1:0]  lbw_rd_rq_struct;

But there are a number of other problems.

It’s legal to have multiple continuous assignments to wires. However, your hierarchical references are not valid. it should be

dut.lbw_rd_rq_struct[0].payload[4]
dut.lbw_rd_rq_struct[1].payload[4]

But you probably want a force instead of a assign so that the 1 and 0 values are not in contention with other drivers on the input.

initial begin
    force dut.lbw_rd_rq_struct[0].payload[4] = 1'b1;
    force dut.lbw_rd_rq_struct[0].payload[5] = 1'b0;
end
1 Like
3

hi dave,
sorry for the sytanx error, whatever you said is correct.
when i am using below
assign dut.lbw_rd_rq_struct[0].payload[4] ='1b1;
assign dut.lbw_rd_rq_struct[0].payload[5]=1’b1;
it is throwing the error but when i am using the force then it is not throwing the errors.