Hi All,
I am connecting the ports of my testbench which is written in UVM and my DUT which is in System verilog.
the way I am connecting is as below:
scheduler_top sch(.clock(clock),
.reset(reset),
.header(in0.header),
.addr(in0.addr),
.data(in0.data),
.rw_en(in0.rw_en));
I am getting few warnings as :
.header(in0.header),
|
ncelab: *W,CUVMPW (./top_dut.sv,30|37): port sizes differ in port connection (8/1).
.addr(in0.addr),
|
ncelab: *W,CUVMPW (./top_dut.sv,31|33): port sizes differ in port connection (29/1).
.data(in0.data),
|
ncelab: *W,CUVMPW (./top_dut.sv,32|33): port sizes differ in port connection (64/1).
I have used structure data types in my DUT and connecting with the top module as below:
module scheduler_top (input clock,
input reset,
//Core requests signals
input header,
input addr,
input data,
input rw_en);
assign cpu_in[101:94] = header;
assign cpu_in[93:65] = addr;
assign cpu_in[64:1] = data;
assign cpu_in[0] = rw_en;
This is how my structure looks like
typedef struct packed{
logic [7:0] header;
logic [28:0] addr;
logic [63:0] data;
logic rw_en;
}cpu_req_type ;
But ‘x’ is propagated throughout my dut. It is not taking the values which is send by the testbench.
Any suggestions are welcome.
Thanks,
Leela