Hi,
I am trying to simulate the following code.
These are my files.
dut.v
module dut(input clk, input logic inp, output logic out);
always @(posedge clk)
begin
out <= inp;
end
endmodule
intf.sv
interface intf(input clk, inp, out );
clocking master_cb @(posedge clk);
output inp;
input out;
endclocking
clocking slave_cb @(posedge clk);
input inp;
output out;
endclocking
endinterface
class.sv
class CC;
virtual intf VIF;
function assign_vi(virtual interface intf IF);
VIF = IF;
endfunction
task run();
@(VIF.master_cb); VIF.master_cb.inp <= 1;
@(VIF.master_cb); VIF.master_cb.inp <= 0;
@(VIF.master_cb); VIF.master_cb.inp <= 1;
endtask
endclass
top.sv
module top();
logic clk;
initial
begin
clk = 0; forever #1 clk = ~clk;
end
CASE_1
dut I_dut (.clk(clk), .inp(I_intf.inp), .out(I_intf.out));
intf I_intf(.clk(clk));
CASE_2
// dut I_dut (.clk(clk));
// intf I_intf(.clk(clk), .inp(I_dut.inp), .out(I_dut.out));
CC CC_inst;
initial
begin
CC_inst = new();
CC_inst.assign_vi(I_intf);
CC_inst.run();
end
initial
begin
#20 $finish();
end
endmodule
In the top.sv file I have 2 CASES corresponding to 2 ways of connecting DUT and Interface.
What is the difference between CASE_1 and CASE_2 ?
Thanks.